Snap Inc. Verified 34h ago
Integrated Circuit Design Verification Engineer
Vancouver, WA - 805 Broadway On-site
$173,000–$259,000 a yearPay$173,000–$259,000
TypeFull-time
Work settingOn-site
Verified listing
JobFig found this opening at its original source and checks that it remains available.
About the role
We’re looking for a Integrated Circuit Design Verification Engineer to join the Spectacles Team at Snap Inc! This position is eligible for equity in the form of RSUs.
What you'll bring
- Strong knowledge of UVM and SystemVerilog for advanced verification methodologies
- Strong knowledge of digital functional simulation, and tools such as Siemens Questa
- Strong knowledge of good Verilog RTL coding practices
- Scripting and automation, such as TCL, Make, Perl, Python and Shell scripts in Linux environment
- Excellent written and verbal English communication
- BSEE or MSEE or relevant years of experience
- 10+ years of experience in ASIC Design Verification
- Experience with entire verification process from planning to sign-off
- Experience with Siemens’ UVM Framework
- Experience in emulation
- Experience in RTL design
- Familiarity with video and display systems, MIPI, AMBA, I2C, SPI protocols and embedded microcontroller
Benefits
Medical InsuranceParental Leave