Jobs in Cupertino, CA

About the role

We are seeking an experienced IC Package Design Engineer to drive and own all aspects of substrate layout and package design work. The ideal candidate will have extensive experience with advanced packaging technologies such as CoWoS, large-scale BGA designs, and package warpage mitigation strategies. You will play a key role in ensuring the mechanical and electrical integrity of packages that power the next generation of AI hardware.

What you'll bring

• Bachelor’s or Master’s degree in Electrical Engineering, Mechanical Engineering, or related discipline
• 5+ years of experience in advanced IC package design, including CoWoS or equivalent technologies
• Proven experience in substrate layout and BGA package design for large ball arrays (>4000 balls) with >20Ghz signaling and >500W
• Strong understanding of stiffener design, open vs. closed package requirements, and package warpage and coplanarity challenges across various sizes
• Proficiency in package design tools such as Cadence APD/SIP, Mentor Xpedition, or similar
• Familiarity with mechanical stress analysis, simulation, and validation methodologies
• Solid communication skills to work across multi-disciplinary teams and external partners
• Experience with advanced packaging nodes (e.g., 2.5D/3D stacking)
• Knowledge of thermal management techniques in package design
• Previous experience working in AI, HPC, or semiconductor design companies

Benefits