Design Verification Engineer
Palo Alto, California, United StatesAll locationsPalo Alto, California, United StatesNew York City, New York, USALondon, England, United Kingdom Hybrid
$200–$400,000 a yearJobFig found this opening at its original source and checks that it remains available.
About the role
As a Design Verification Engineer at Normal, you will verify our own physics-inspired ASICs on the road to tapeout, and set the quality bar for what our AI learns: reviewing generated verification collateral and shaping the standards our models train against. From time to time, you may also be tapped to support a customer deployment alongside our forward-deployed team, where your verification credibility helps our AI platform land inside real DV flows. The through-line is your DV expertise, applied to silicon that computes differently than anything you've verified before, and to the AI that is changing how verification gets done. This is a seat for a verification engineer who wants their craft to compound rather than repeat.
What you'll bring
- 5+ years of experience in digital verification at a major semiconductor or EDA tool company
- Advanced proficiency in SystemVerilog, UVM methodology, and EDA verification tools (vManager, Xcelium, Jasper), with strong Python or Perl scripting
- Proven expertise in end-to-end design verification, including test plan creation, stimulus generation, and feature extraction
- Willingness to occasionally support customer-facing deployment work, including some travel
- Excellent written and spoken communication skills: you can hold the room with a customer's verification lead as credibly as you hold a debug session
- Experience in a customer-facing, field-application, or forward-deployed engineering role at a semiconductor or EDA company
- Hands-on use of LLMs or agentic tools in verification workflows
- Exposure to analog, mixed-signal, or unconventional compute verification