Senior Static Timing Analysis (STA) Methodology Engineer
Saratoga, CA On-site
$120,000–$220,000 a yearJobFig found this opening at its original source and checks that it remains available.
About the role
We are seeking a Senior STA Methodology Engineer to join our ASIC design team. In this role, you will own cross-functional timing methodology efforts across multiple IPs, projects, and technology nodes for our cutting-edge SoC designs targeting 5G, IoT, and LEO satellite communication applications. You will architect and maintain production STA flows, drive signoff closure, and introduce data-driven techniques to continuously improve PPA and team productivity. As a member of our team, you will play a crucial role in driving our success. Our team members have a strong sense of dedication and responsibility; this includes a strong commitment to our mission to create an entirely new suite of global capabilities to improve lives, business efficiencies and build a smarter planet. This means that there will be times when extra hours, including nights and weekends, may be needed to meet critical deadlines and mission goals. In return, we offer a dynamic work environment with opportunities for professional growth and development and the chance to make a meaningful impact in a high-growth industry.
What you'll bring
- BS or MS in Electrical or Computer Engineering, or equivalent industry experience
- 8+ years of industry experience in STA and timing methodology, focused on high-performance and low-power designs at advanced technology nodes
- Deep knowledge of STA tools and techniques, including noise, crosstalk, OCV, AOCV, POCV, and LVF analysis
- Fluency with PrimeTime and related signoff tools (PT-SI, PTPX, PT-ECO), with extensive hands-on experience driving signoff correlation and closure
- Strong expertise in debugging timing constraints and resolving timing correlation issues across complex SoC designs
- Experience with MMMC analysis, timing ECO flows, and late-stage timing closure techniques
- Proficiency in writing robust, production-quality scripts in Tcl, Python, and/or Perl for CAD utilities and flow components
- Solid knowledge of clock tree synthesis (CTS) and its interaction with timing analysis
- Excellent communication and collaboration skills for cross-functional, multi-project environments
- Experience with advanced process nodes (7nm, 5nm, or below)
- Familiarity with low-power design methodologies and their timing implications (DVFS, power gating)
- Exposure to interface protocol timing (DDR, PCIe, USB, SerDes)