Staff DV Engineer
Saratoga, CA On-site
$120,000–$220,000 a yearJobFig found this opening at its original source and checks that it remains available.
About the role
We are seeking Digital Design Verification Engineers to verify our custom ASICs for satellite and wireless telephony. Knowing Verilog, SystemVerilog, and UVM is a must, VHDL is valuable. We prioritize AI assistance to accelerate work. As a member of our team, you will play a crucial role in driving our success. Our team members have a strong sense of dedication and responsibility; this includes a strong commitment to our mission to create an entirely new suite of global capabilities to improve lives, business efficiencies and build a smarter planet. This means that there will be times when extra hours, including nights and weekends, may be needed to meet critical deadlines and mission goals. In return, we offer a dynamic work environment with opportunities for professional growth and development and the chance to make a meaningful impact in a high-growth industry.
What you'll bring
- HDL & Verification Methodology
- · Strong proficiency in Verilog and SystemVerilog
- · Experience writing tests within an existing UVM verification environment
- · Solid understanding of UVM architecture and methodology
- 6+ years of design verification experience in the semiconductor industry
- This is a full time, exempt position, based out of our Saratoga office.
- The total compensation packaged will be determined by various factors such as your relevant job-related knowledge, skills, and experience.
- We are redefining how satellites are designed, manufactured and used—so we’re looking for candidates with passion, deep knowledge and direct experience on LEO satellite component development, design and in-orbit activities.
- If that’s your experience – then we’ll be immediately wow-ed.