Jobs in Palo Alto, CA

About the role

This position performs finite element analysis for CspeedIO optical engine packages across both thermal and structural domains. It is scoped for a strong FEA engineer: demonstrated depth in either thermal or mechanical analysis is expected, and the ability to work competently in the other is required. The analysis supports package architecture decisions and qualification. Temperature governs optical wavelength and channel uniformity. Deformation and interconnect stress govern assembly yield, reliability, and optical coupling, since warpage displaces optical facets. Both sets of results terminate in the same design decisions, which is why the scope is held in one role. Correlation against measured hardware is a standing expectation. Results are used for design sign-off, so assumptions must be documented and defensible.

What you'll bring

• MS or PhD in Mechanical Engineering, Materials Science, Engineering Mechanics, or equivalent practical background.
• 6+ years of finite element analysis for semiconductor packaging or electronic systems, including one product carried from architecture through hardware correlation.
• Expert proficiency in one commercial FEA or CFD tool and working proficiency in a second covering the other domain — for example Ansys Mechanical or Abaqus alongside Icepak, Fluent, Flotherm, or Celsius.
• Sound FEA fundamentals: meshing judgment, boundary condition selection, convergence, and the ability to defend a model rather than only to run one.
• Demonstrated correlation of simulation against physical measurement, and the judgment to distinguish a modeling error from a process excursion.
• Experience with advanced packaging construction: flip chip, 2.5D/3D, interposers, and heterogeneous integration.
• Depth in nonlinear and time-dependent material behavior: creep, viscoplasticity, viscoelasticity, and fatigue.
• Silicon photonics or optoelectronic packaging, including thermo-optic sensitivity or warpage as an optical alignment constraint.
• Coupled thermal-structural workflows, including transfer of a computed temperature field into a structural model.
• Direct-to-chip liquid cooling, or chip-package interaction and low-k dielectric stress.
• Scripting for model automation and parametric studies, and design of experiments methodology.