Jobs in Palo Alto, CA

About the role

We are looking for exceptional physical design engineers to transform our high-performance architectural concepts into production-ready silicon. You will own the physical implementation flow from synthesis through tape-out, pushing the absolute limits of advanced foundry nodes to maximize PPA. You will take ownership of block-level and top-level physical design, collaborating tightly with RTL designers to close timing, electrical, and physical verification for our custom AI accelerator.

What you'll bring

• Bachelor’s degree in Electrical Engineering or Computer Engineering, and 5+ years practical industry experience working with advanced process nodes (7nm or below).
• Deep hands-on proficiency with industry-standard physical design, timing, and sign-off tools (e.g., Innovus, Fusion Compiler, PrimeTime, RedHawk).
• Proven track record running logic synthesis, integrating compiled memory macros, and managing multi-voltage design techniques using power intent specifications (UPF/CPF).
• Exceptional debugging skills with a first-principles approach to navigating complex trade-offs between congestion, timing slack, and power density in highly utilized designs.
• A highly collaborative mindset and a bias for action to push boundaries and co-design effectively with RTL and architecture teams.
• An extensive track record of delivering high-performance SoCs, CPUs, GPUs, or AI accelerators through multiple successful production tape-outs.
• Hands-on experience optimizing physical layouts for highly parallel compute structures, such as systolic arrays, large tensor execution units, or high-bandwidth memory (HBM) interfaces.
• Experience custom-scripting or extending EDA tools (using Tcl, Python, or specialized ML APIs) to automate physical design closure and build bespoke workflow pipelines.

Locations