Principal Design Verification Engineer – CPU Core Frontend
Austin, Texas, United StatesAll locationsAustin, Texas, United StatesSanta Clara, California, United States On-site
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About the role
SiFive is looking for a Principal Design Verification Engineer to lead verification strategy and execution for the CPU Core Frontend in a high-performance out-of-order core. This is a senior tech-lead role for an engineer who can define architecture-aware verification strategy, identify microarchitectural risk early, solve the hardest frontend verification problems, and raise verification quality across the broader CPU DV organization. The primary technical scope of this role is frontend verification, with emphasis on branch prediction, instruction fetch, frontend redirects and recovery, prediction training/update behavior, fetch correctness, and interface interactions across the frontend pipeline. The role requires close partnership with architecture, RTL, performance, and verification teams to ensure design intent is captured correctly and signoff quality is achieved with strong technical judgment and scalable methodology. In addition to base pay, this role may be eligible for variable/ incentive compensation and/ or equity. Any offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.
What you'll bring
- BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
- 12+ years of relevant experience in CPU/core or SoC functional verification, with substantial experience in high-performance CPU verification appropriate for a Principal / T6 role.
- Direct experience with out-of-order CPU core verification and strong understanding of CPU microarchitecture.
- Deep expertise in CPU frontend verification, especially branch prediction and instruction fetch verification.
- Strong knowledge of verification flow methodology, including test planning, stimulus generation, failure analysis, coverage analysis, and coverage closure.
- Strong debug skills and the ability to translate architectural intent into an effective verification strategy and execution plan.
- Strong software and scripting fundamentals for building scalable DV infrastructure, automation, and analysis workflows.
- Experience verifying advanced frontend architectures or decoupled fetch/prediction pipelines in high-performance CPU cores.
- Experience with branch prediction microarchitecture such as BTB-style structures, target prediction, return prediction, global-history-based prediction, predictor training, and misprediction recovery.
- Experience using formal verification to target bounded, control-heavy, or interface-sensitive frontend problems.
- Experience using emulation or other acceleration techniques to improve turnaround on large CPU verification workloads.
- Experience collaborating across architecture, performance, compiler, system verification, and software teams to close verification gaps from multiple perspectives.